Owing to their circuit simplicity and small current consumption, synchronous delay circuits that eliminate clock skew in a short synchronization time find use in high-speed clock synchronizing circuits. Reference may be had to the following literature describing such synchronous delay circuits:
(1) Japanese Patent Kokai publicaiton No. JP-A-8-237091; PA1 (2) "Skew Minimization Technique for 256 M-bit Synchronous DRAM and Beyond", by Jin-Man Han, et al., 1996 Symp. on VLSI Circ., pp. 192.about.193; PA1 (3) "Clock Buffer Chip with Absolute Delay Regulation Over Process and Environment Variations", by Richard B. Watson et al., Proc. of IEEE 1992 (Custom Integrated Circuits Conference), 25.2; and PA1 (4) "Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface", IEICE TRANS. ELECTRON., VOL. E79-C, No. 6, June, 1996, pp. 798.about.807.
As shown in FIG. 9, a synchronous delay circuit basically comprises a delay circuit 901 used to measure a fixed time difference, a delay circuit 902 for reconstructing the measured delay time, and a dummy delay circuit 905 having a delay time corresponding to delay times td1+td2 obtained by adding delay times td1, td2 of an input buffer 903 and clock driver 904.
In order to make the delay time equal to the delay times td1, td2 of the input buffer 903 and clock driver 904, there are many cases where the dummy delay circuit 905 is composed of an input buffer dummy 905A, which uses circuitry exactly the same as that of the input buffer, and a clock driver dummy 905B.
The delay circuits 901 and 902 are constituted by delay circuit chains having equal delay times, and therefore, they are also referred to as delay circuit chains.
The purpose of the delay circuits 901 and 902 is to measure a fixed period of time (this is the function of circuit 901) and reconstruct this period of time (this is the function of circuit 902). This purpose can be attained by causing a signal to advance through the delay circuit 901 and arrange it so that a number of delay elements equal to the number of delay elements through which the signal passed in the delay circuit 901 will be traversed by the signal in the delay circuit 902.
Methods for arranging the number of delay elements equal to the number of delay elements through which the signal passed in the delay circuit 901 will be traversed by the signal in the delay circuit 902 can be divided into two categories depending upon the propagation directions of the delay circuits 901 and 902 and into two categories depending upon whether the end is selected or the overall path in order to decide the length of the delay circuit 902. There are four types in each of the two categories.
More specifically, if the methods are classified depending upon the propagation directions of the delay circuits 901 and 902, they are considered as the types shown in FIGS. 12 and 13 in which the propagation directions of the delay circuits 901 and 902 are the same and length is decided on the output terminal side of the delay circuit 902 in order to decide the number of elements in the delay circuit 902, and there are the types shown in FIGS. 10 and 11 in which the propagation directions of the delay circuits 901 and 902 are opposite each other and length is decided on the input terminal side of the delay circuit 902 in order to decide the number of elements in the delay circuit 902.
If the methods are classified depending upon whether the end is selected or the overall path in order to decide the length of the delay circuit 902, there are the methods shown in FIGS. 10 and 13 in which the end is selected and the methods shown in FIGS. 11 and 12 in which the overall path is selected.
FIG. 10 corresponds to the scheme described in the above-mentioned Japanese Patent Application Laid-Open No. 8-237091 filed by the present inventor.
FIG. 11 corresponds to the scheme described in the above-mentioned literature (4) (IEICE TRANS. ELECTRON., VOL. E79-C, No. 6, June, 1996, pp. 798.about.807).
FIG. 12 corresponds to the scheme described in the above-mentioned literature (2) (1996 Symp. on VLSI Circ., pp. 192.about.193).
FIG. 13 corresponds to the scheme described in the above-mentioned literature (3) (Proc. of IEEE 1992 CICC 25.2) and in the above-mentioned literature (2) (1996 Symp. on VLSI Circ., pp. 112.about.113).
Operations through which clock skew is eliminated will be described with reference to the schematic views and timing charts of FIGS. 14 and 15.
(1) Clock Delay when Synchronous Delay Circuit is Not Used
FIG. 14 illustrates when a synchronous delay circuit is not used. As shown in FIG. 14(a), an external clock 906 is utilized as an internal clock 907 supplied to the internal circuitry of a semiconductor integrated circuit device through the input buffer 903 and the clock driver 904. The delay time between the external clock 906 and the internal clock 907 is decided by the delay time td1 of the input buffer 903 and the delay time td2 of the clock driver 904. The sum td1+td2 is clock skew.
(2) Principle of Clock Delay Elimination when Synchronous Delay Circuit is Used
A synchronous delay circuit uses a clock pulse enters at a clock period tCK to effectively eliminate clock skew. That is, a delay circuit having a delay time of EQU tCK-(td1+td2)
is provided and disposed between the input buffer (delay time td1) and the clock driver (delay time td2) so that the sum of the delay times are equal to the clock period tCK [=td1+tCK-(td1+td2)+td2].
As a result, the timing of the internal clock output by the clock driver becomes equal to the timing of the external clock.
(3) Method of Clock Delay Elimination when Synchronous Delay Circuit is Used
FIG. 15(b) shows a timing chart when a synchronous delay circuit is actually used.
The operation of a synchronous delay circuit requires two periods.
The first period is used to measure the delay time tCK-(td1+td2) dependent upon the clock period and to decide the delay length of the delay circuit that reconstructs the delay tCK-(td1+td2).
The next period is used for the amount of delay of tCK-(td1+td2).
With regard to the first period, the dummy delay circuit 905 of the clock driver 904 and the delay circuit chain 901 are used to measure the delay time tCK-(td1+td2) dependent upon the clock period.
The output of input buffer 903 resulting from the first pulse of two consecutive pulses of external clock 906 is caused to advance through dummy delay circuit 905 and delay circuit 901 in one clock period tCK, which extends up to output of the second pulse from the input buffer 903. Since the delay time of the dummy delay circuit 905 is td1+td2, the time needed for a pulse to advance through the delay circuit 901 is tCK-(td1+td2).
The delay time of the delay circuit 902 is set to be equal to the time tCK-(td1+td2) that was required for the pulse to advance through the delay circuit 901.
Although this method of setting the delay circuit 902 can be classified broadly into the four types mentioned above, each is capable of attaining the desired object.
With regard to the next period, a clock pulse that has been output by the input buffer 903 passes through the delay circuit 902 whose delay is tCK-(td1+td2) and is output by the clock driver 904 to thereby produce the internal clock 907 whose delay is exactly equal to the clock cycle tCK.
The process described above provides the internal clock 907, which is free of clock skew, in two clock periods.
Meanwhile, in a synchronous delay circuit adapted for removing clock skew in a shorter synchronous period, there has already been proposed a system configured not only for eliminating skew but also for doubling the clock frequency or generating 50% duty (Duty50) shown for example in JP Patent Kokai JP-A-8-237091 of the above publication [1] by the inventors hereof.
Similarly to the skew eliminating configuration, the circuit for doubling the clock frequency (frequency doubling circuit) and for generating Duty50 is made up of paired delay circuits, namely a delay circuit for measuring a pre-set time difference and a delay circuit for reproducing the delay time, and is configured for doubling the delay time of the delay circuit for reproducing the delay time to a speed twice as high as that of the delay circuit for measuring the pre-set time difference. In actuality, the circuit for doubling the clock frequency and for generating Duty50 is frequently used in combination with the skew eliminating circuit.
FIG. 25 shows an example of a basic configuration of a synchronous delay circuit. Referring to FIG. 25, this conventional synchronous delay circuit is a conventional synchronous delay circuit, explained with reference to FIG. 9. The synchronous delay circuit shown in FIG. 25 further comprises a pair of delay circuit chains, made up of a delay circuit chain 901 for measuring the clock period, and a delay circuit chain 902 for reproducing the measured delay time, and a pair of delay circuit chains, made up of a delay circuit chain 901A for measuring the pre-set time difference and a delay circuit chain 902A for reproducing the measured delay time (speed-doubling delay circuit chain), with the two pairs of the delay circuit chains being connected in series with each other. An output of the delay circuit chain 902 and an output of the speed-doubling delay circuit chain 902A are synthesized by a synthesis circuit 910A so as to be supplied to a clock driver 904 with delay time td2.
This double frequency generating and Duty50 generating circuit may be classified similarly to the skew removing circuit.
The operation of the double frequency generating and Duty50 generating circuit is explained with reference to a timing chart shown in FIG. 26.
(4) Principle of Clock Delay Removal in Case of Using the Synchronous Delay Circuit
For generating the double frequency and Duty50 circuits, the synchronous delay circuit utilizes the properties of the clock pulses being entered every clock period tCK. That is, a double speed delay circuit chain (902A of FIG. 25) with a delay time of tCK/2 is provided and the delay time with respect to the pre-input clock is set so as to be equal to one-half the clock period tCK. The clock signals so set are then synthesized with the original clock signals (output C of the delay circuit chain 902 of FIG. 25) to provide the double frequency (E of FIG. 25) or Duty50%.
(5) Method for Removing Clock Delay in Case of using the Synchronous Delay Circuit
The timing operation in case of using the synchronous delay circuit is explained with reference to FIG. 26, which shows a timing chart representing the waveform of each node of FIG. 25.
The operation of the synchronous delay circuit for double frequency generation and Duty50 generation needs of 1.5 periods.
The first one period is used for measuring the delay time tCK which depends on the clock period and for determining the delay length of the delay time adapted for reproducing the delay amount of tCK/2. The next period is used for the delay amount of tCK/2.
In measuring the clock-period-dependent delay time tCK for the first period, a delay circuit chain 901A is used. An output of the first pulse delay circuit chain 902 for the first one of two consecutive pulses of the clocks 906 (C of FIGS. 25 and 26) proceeds through the delay circuit chain 901A during one clock period tCK until outputting of the second delay circuit chain 902. That is, the time during which the pulse proceeds through the delay circuit chain 901A represents the clock period tCK.
The delay time of the delay circuit chain 902A is set so as to be equal to one-half tCK which is the time during which the pulse proceeded through the delay circuit chain 901A.
The methods for setting the delay time of the delay circuit chain 902A are roughly classified into four types according to desired objectives to be achieved.
During the next period, the clocks exiting the delay circuit chain 901A are output through the delay circuit chain 902A having the delay quantity equal to tCK/2 (signal D of FIGS. 25 and 26) so as to be synthesized with the clock exiting the delay circuit chain 902 (signal C of FIGS. 25 and 26) and output to generate internal clocks 907 of the double frequency and internal clocks of the Duty50 (907A of FIG. 26).
By the above process, two clock periods for clock skew removal and 1.5 periods for double frequency and Duty50, totaling at 3.5 periods, provide internal clock double frequency free of clock skew and clocks of Duty50 are produced.
However, this conventional synchronous delay circuit execute clock skew removal and frequency doubling--Duty50 with two clock periods and with 1.5 periods, respectively, thus requiring 3.5 clocks (3.5 tCK) as the time required for skew removal.